1. Field of the Invention
The present invention relates to a CMOS dynamic circulating-one shift register and, more particularly, to a circulating-one shift register which is completely self-contained, requiring only a single external clock to guarantee a single circulating one, after power-up or during long-term operation, for a shift register of any desired length.
2. Description of the Prior Art
Many digital control functions require the capability to sequentially select a number of events or operations in a repetitive pattern. A standard design for implementing such a selection process utilizes a counter/decoder configuration. The amount of logic used in this arrangement represents an overdesign and requires a larger silicon area than is necessary to provide the sequential selection function. In particular, the overdesign is related to the fact that: (1) conventional decoders accept a random binary input and produce a well-defined output not needed in a repetitive operation; (2) the counter is an additional level of complexity which is not required to produce the sequential operation; and (3) the counter/decoder circuit is completely static, a feature not necessary for the repetitive selection application.
One prior art arrangement which overcomes some of these problems is discussed in the article "One NOR Gate Starts Shift-Register Loop", by Jean-Pierre Dujardin appearing in Electronics, Apr. 3, 1975, at page 103. In the Dujardin circuit, the output from each stage of a shift register is applied as an input to a NOR gate. The output from the NOR gate is fed back to the input of the first stage of the shift register. Therefore, when the output from each shift register stage is equal to a logic 0, the output from the NOR gate will be a logic 1, which is transferred on the next clock pulse to the output of the first stage. So long as only one stage of the shift register has an output signal of a logic 1, the output of the NOR gate will remain a logic 0 and will not affect the cycling of the single logic 1. This circuit requires no external timing to introduce the single logic 1 into the loop and no subsequent resetting. However, the Dujardin arrangement becomes an unacceptable alternative when a large number of stages are included in the shift register, requiring an extremely substantial amount of silicon to lay out the circuit. For example, a 24-stage shift register loop formed using this design would require a 23-input NOR gate, which in CMOS technology translates to approximately 46 MOS transistors, 23 transistors connected in series and 23 transistors connected in parallel.
There remains a need, therefore, for a circulating-one shift register which includes the benefits of the Dujardin arrangement (for example, requiring only a single external clock) and yet may also include any number of individual stages without requiring an unacceptable amount of silicon.